1. Field of the Invention
The present invention relates to a ladder resistor built into either a successive approximation analog-to-digital converter or ADC or a digital-to-analog converter or DAC used to control a machine system such as a servo-controlled machine.
2. Description of the Prior Art
FIG. 6 is a schematic circuit diagram showing the structure of a prior art ladder resistor as disclosed in Japanese patent application publication (TOKKAIHEI) No. 11-145835. FIG. 7 is a block diagram showing the structure of a successive approximation ADC having a ladder resistor with 6-bit resolution as shown in FIG. 6.
In FIG. 6, reference numeral 110 denotes a normal resistor group including 64 resistors R0A to R63A connected in series, and reference numeral 120 denotes a reverse resistor group including the same number of resistors R0B to R63B connected in series as the plurality of resistors R0A to R63A included in the normal resistor group 110, the plurality of resistors R0B to R63B corresponding to the plurality of resistors R0A to R63A, respectively. The plurality of resistors R0A to R63A included in the normal resistor group 110 and the plurality of resistors R0B to R63B included in the reverse resistor group 120 are formed so that they have the same size. Each of the normal resistor group 110 and the reverse resistor group 120 divides the difference between two fixed voltages VRT and VRB applied thereto from outside the successive approximation ADC or generated in the ADC into 64 (=26) steps. Each of the normal resistor group 110 and the reverse resistor group 120 can thus generate and output 64 reference voltages by way of its 64 taps (i.e., 64 nodes).
In addition, the normal resistor group 110 is divided into four resistor sets each of which contains 16 resistors, as shown in FIG. 6. These four resistor sets are arranged so that they run in parallel with one another. Similarly, the reverse resistor group 120 is divided into four resistor sets each of which contains 16 resistors, as shown in FIG. 6. These four resistor sets are arranged so that they run in parallel with one another. Furthermore, the four resistor sets of the reverse resistor group 120 and the four resistor sets of the normal resistor group 110 are alternately aligned in the direction of X of FIG. 6.
In addition, each resistor included in the normal resistor group 110 and a corresponding resistor included in the reverse resistor group 120, that is, each resistor pair is arranged so that the two resistors included in each resistor pair are symmetric with respect to the center C of the layout of the ladder resistor. In other words, such the two resistors as R0A and R0B, R1A and R1B, . . . , or R63A and R63B included in each resistor pair are symmetric with respect to the center C of the layout of the ladder resistor.
Furthermore, in FIG. 6, reference numeral 130A denotes a first 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the first resistor set (R0A to R15A) of the normal resistor group 110 and a plurality of taps of the first resistor set (R0B to R15B) of the reverse resistor group 120, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral 130B denotes a second 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the second resistor set (R16A to R31A) of the normal resistor group 110 and a plurality of taps of the second resistor set (R16B to R31B) of the reverse resistor group 120, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral 130C denotes a third 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the third resistor set (R32A to R47A) of the normal resistor group 110 and a plurality of taps of the third resistor set (R32B to R47B) of the reverse resistor group 120, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral 130D denotes a fourth 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the fourth resistor set (R48A to R63A) of the normal resistor group 110 and a plurality of taps of the fourth resistor set (R48B to R63B) of the reverse resistor group 120, and for furnishing a reference voltage which appears at the selected input terminal, and reference numeral 140 denotes a 4-to-1 selector for selecting one output from the outputs of the first through fourth 16-to-1 selectors 130A to 130D. The first through fourth 16-to-1 selectors 130A to 130D and the 4-to-1 selector 140 are controlled by a latch/control circuit 700 shown in FIG. 7.
In FIG. 7, reference numeral 300 denotes a sample and holding circuit (abbreviated as S/H from here on) for holding an analog voltage applied thereto by way of an analog input terminal 200 while a 1-bit comparator 600 compares the analog voltage with a threshold voltage, and reference numeral 400 denotes a DAC that is controlled by the latch/control circuit 700, and that delivers a reference voltage from the ladder resistor 100 or a voltage generated based on the reference voltage to a subtracter 500 as a voltage to be compared. The 1-bit comparator 600 determines whether or not the subtraction result from the subtracter 500 is 0 or more, and then outputs xe2x80x9c1xe2x80x9d if the subtraction result is 0 or more, and outputs xe2x80x9c0xe2x80x9d otherwise. The subtracter 500 subtracts the voltage to be compared from the DAC 400 from the analog voltage output from the S/H 300, and then outputs the subtraction result to the 1-bit comparator 600. The latch/control circuit 700 latches the output of the 1-bit comparator 600, and delivers a control signal for determining the voltage to be compared that should be output next by the DAC 400 based on the output of the 1-bit comparator 600 to the DAC 400, and then furnishes an A/D conversion result to outside the successive approximation ADC by way of an output terminal 800.
In operation, the ladder resistor 100 divides the difference between two fixed voltages VRT and VRB applied thereto from outside the successive approximation ADC or generated in the ADC into 64(=26) steps. The ladder resistor 100 can thus generate 64 reference voltages, and select one of them and output the selected reference voltage to the DAC 400. Each of the first through fourth 16-to-1 selectors 130A to 130D is controlled by the control signal from the latch/control circuit 700 as shown in FIG. 7. Each of the first through fourth 16-to-1 selectors selects one reference voltage from 16 reference voltages generated by the corresponding resistor set and outputs the selected reference voltage. The 4-to-1 selector 140 is similarly controlled by the control signal from the latch/control circuit 700, and selects one reference voltage from four reference voltages selected by the first through fourth 16-to-1 selectors 130A to 130D and outputs the selected reference voltage to the DAC 400. The ladder resistor 100 thus outputs one reference voltage selected by the latch/control circuit 700 to the DAC 400.
On the other hand, the S/H 300 is holding an analog voltage applied thereto by way of the analog input terminal 200 while the 1-bit comparator 600 compares the analog voltage with a threshold voltage. The DAC is controlled by the latch/control circuit 700, and delivers a reference voltage from the ladder resistor 100 or a voltage generated based on the reference voltage to the subtracter 500 as a voltage to be compared. The subtracter 500 subtracts the voltage to be compared from the DAC 400 from the analog voltage output from the S/H 300, and then outputs the subtraction result to the 1-bit comparator 600.
The 1-bit comparator 600 determines whether or not the subtraction result from the subtracter 500 is 0 or more, and then outputs xe2x80x9c1xe2x80x9d if the subtraction result is 0 or more, and outputs xe2x80x9c0xe2x80x9d otherwise. The latch/control circuit 700 latches the output of the 1-bit comparator 600, and delivers a control signal for determining the voltage to be compared that should be output next by the DAC 400 based on the output of the 1-bit comparator 600 to the DAC 400. After repeating such processing, the 1-bit comparator 600 obtains and furnishes an A/D conversion result to outside the successive approximation ADC by way of the output terminal 800. This exemplary ADC selects one reference voltage from among the plurality of reference voltages generated by the ladder resistor, and employs a 1-bit comparator. As an alternative, the ADC can be so constructed as to select two or more reference voltages from among the plurality of reference voltages generated by the ladder resistor and provide the same advantage.
The ladder resistor 100 as shown in FIG. 6 is generally formed on a semiconductor substrate. The plurality of resistors R0A to R63A included in the normal resistor group and the plurality of resistors R0B to R63B included in the reverse resistor group are so formed on a semiconductor substrate as to have the same resistance according to a given manufacturing process, and those resistors in each resistor group are connected in series with aluminum wiring, so that the ladder resistor 100 is formed on the semiconductor substrate. It is desirable that the plurality of resistors formed in the ladder resistor have the same resistance. Actually, the resistances of the plurality of resistors are not completely identical with one another because of a variation in the parameters for the manufacturing process, such as the impurity concentration etc. (this phenomenon is referred to as mismatch from here on). The semiconductor chip is bonded to a die pad using resin or the like. Distortions due to stresses caused by bonding can thus cause the uniformity in the resistances of the plurality of resistors included in the ladder resistor. In addition, mismatch is also caused by stresses due to heat because the die pad, resin, and chip that constitute the semiconductor chip are made of different materials having different coefficients of thermal expansion, respectively. In general, either a dummy resistor or a dummy pattern to reduce such a mismatch is disposed in the ladder resistor.
The ladder resistor 100 as shown in FIG. 6 is expected to solve the problem that arises in the prior art. By counterbalancing the influence of distortions due to stresses in the direction of X and the influence of distortions due to stresses in the direction of Y on the resistances of the plurality of resistors that constitute the ladder resistor, the ladder resistor generates a plurality of reference voltages having a theoretical value or a value close to the theoretical value.
A problem with the prior art ladder resistor constructed as above is that since wiring for the normal resistor group 110 and wiring for the reverse resistor group 120 cross each other at many points, for example, wiring for connecting the taps of the reverse resistor group 120 to the first through fourth 16-to-1 selectors and wiring for connecting resistors included in the normal resistor group 110 to each other cross each other, as shown in FIG. 6, and those pieces of wiring interfere with each other, the plurality of reference voltages cannot be generated with a high degree of accuracy.
Furthermore, in the prior art ladder resistor constructed as shown in FIG. 6, the normal resistor group 110 and the reverse resistor group 120 are both divided into an even number of resistor sets, respectively. When an analog voltage whose value changes continuously such that its equivalent digital value changes at most bits when incremented by 1, e.g., an analog voltage having an equivalent digital value that varies from 1 Fh to 20 h is input to the successive approximation ADC, since the 32nd tap corresponding to 1 Fh and the 33rd tap corresponding to 20 h are included in different resistor sets, respectively, and therefore wiring 150 shown in FIG. 6 to connect these different resistor sets to each other is longer than wiring to connect resistors included in each resistor set to each other, the reference voltage that appears at the 33rd tap of the ladder resistor deviates from its theoretical value due to a parasitic resistance in the wiring to connect the different resistor sets to each other. In other words, in the prior art ladder resistor constructed as shown in FIG. 6, when an analog voltage having a corresponding A/D conversion result that varies at most bits thereof when incremented by 1 is input to the ADC, there causes distortions in the A/D conversion result because a corresponding reference voltage generated deviates from its theoretical value due to a parasitic resistance in the wiring to connect different resistor sets to each other.
The present invention is proposed to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a ladder resistor capable of preventing wiring associated with a normal resistor group included therein and wiring associated with a reverse resistor group included therein from interfering with each other, and generating a plurality of reference voltages with a high degree of accuracy.
It is another object of the present invention to provide a ladder resistor capable of generating a plurality of reference voltages with a high degree of accuracy even when an analog voltage having a corresponding A/D conversion result that varies at most bits thereof when incremented by 1 is input to a successive approximation ADC or the like into which the ladder resistor is incorporated.
In accordance with an aspect of the present invention, there is provided a ladder resistor for generating a plurality of reference voltages, and for selecting and outputting one or more desired reference voltage from among the plurality of reference voltages, the ladder resistor comprising: a first resistor group including a number of resistors connected in series and generating a number of reference voltages; and a second resistor group including a same number of resistors connected in series as the plurality of resistors included in the first resistor group, and generating a number of reference voltages, the plurality of resistors included in the second resistor group corresponding to the plurality of resistors included in the first resistor group, respectively, each of the plurality of resistors included in the first resistor group and a corresponding one of the plurality of resistors included in the second resistor group, that is, each resistor pair being symmetric with respect to a given point, and the first resistor group being separated from the second resistor group so that they face each other with the point between.
In accordance with a preferred embodiment of the present invention, the ladder resistor further comprises a reference voltage selection unit for selecting one tap from among a plurality of taps disposed in the first resistor group and selecting a corresponding tap from among a plurality of taps disposed in the second resistor group, and for, after that, electrically connecting the selected tap of the first resistor group to the selected tap of the second resistor group so as to selectively output one of the plurality of reference voltages generated. Preferably, the reference voltage selection unit includes a first selector for selecting one tap from among the plurality of taps disposed in the first resistor group, and a second selector for selecting a corresponding tap from among the plurality of taps disposed in the second resistor group, and the first and second selectors are symmetric with respect to the given point.
In accordance with another preferred embodiment of the present invention, the ladder resistor further comprises a first constant voltage supply unit for supplying a first constant voltage to one end of the first resistor group, a second constant voltage supply unit for supplying a second constant voltage to another end of the first resistor group, a third constant voltage supply unit for supplying the first constant voltage to one end of the second resistor group, and a fourth constant voltage supply unit for supplying the second constant voltage to another end of the second resistor group, wherein the first and third constant voltage supply units are symmetric with respect to the given point and the second and fourth constant voltage supply units are symmetric with respect to the given point.
In accordance with another preferred embodiment of the present invention, the plurality of resistors included in each of the first and second resistor groups are divided into an odd number of resistor sets arranged in parallel with one another, and each of the first and second resistor groups is provided with at least one dummy resistor connected in series to the plurality of resistors included in each of the first and second resistor groups so that each of the odd number of resistor sets has an identical number of resistors.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.